![]() ![]() Design data such as waveforms and coverage in functional verification, physical layout shapes, timing/power/voltage/variation analysis reports, design RTL, netlist and SDC specifications in design implementation.With the new Cadence JedAI Platform, engineers can seamlessly manage both structured and unstructured data, including: With the Cadence JedAI Platform, Cadence is unifying big data analytics across its AI platforms-Verisium verification, Cadence Cerebrus implementation, and Optimality system optimization-as well as third-party silicon lifecycle management systems. ![]() The Cadence JedAI Platform enables engineers to glean actionable intelligence from massive volumes of chip design and verification data, opening the door to a new generation of AI-driven design and verification tools that dramatically improve productivity and power, performance and area (PPA). has announced the delivery of the Cadence Joint Enterprise Data and AI (JedAI) Platform, enabling a generational shift from single-run, single-engine algorithms in electronic design automation (EDA) to algorithms that leverage big data and artificial intelligence (AI) to optimize multiple runs of multiple engines across an entire SoC design and verification flow. ![]()
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